1. Field of the Invention
The present invention relates to an element for evaluation (hereinafter, referred to as TEG (Test Element Group)) for evaluating characteristics of a thin film transistor (Thin Film Transistor: hereinafter, referred to as TFT). In addition, the present invention relates to a manufacturing method of the TEG, an evaluation method of electronic characteristics in a semiconductor device using the TEG, and a semiconductor device that is evaluated using the TEG.
2. Description of the Related Art
Since a conventional thin film transistor (TFT) is formed of an amorphous semiconductor film, it is almost impossible to obtain a TFT having field effect mobility of 10 cm2/V·sec or more. However, a TFT having high field effect mobility can be obtained owing to the appearance of a TFT formed of a crystalline semiconductor film.
Since the TFT formed of a crystalline semiconductor films has high field effect mobility, various functional circuits can be formed over the same substrate simultaneously by using the TFT. For example, in a display device, previously, a driver IC and the like are mounted on a display portion to have a driver circuit. On the other hand, the use of the TFTs formed of crystalline semiconductor films enables a display portion and a driver circuit formed of a shift register circuit, a level shifter circuit, a buffer circuit, a sampling circuit, and the like to be disposed over the same substrate. The driver circuit is basically formed by a CMOS circuit including an N-channel TFT and a P-channel TFT. In order to obtain high on current drive capacity in the driver circuit, it is necessary to secure a sufficiently large on current.
There is a method for reducing parasitic resistance of a TFT as a method for improving on characteristics. Specifically, parasitic resistance is reduced by providing metal silicide in source and drain regions (see Reference 1: Japanese Patent Application Laid-Open No. H10-98199).
In the case where metal silicide is formed in the source and drain regions, the metal silicide is formed over a surface of an impurity region of silicon (Si) and a contact region of the metal silicide and Si is formed. At this time, when the impurity region of Si has high resistance, the contact region of the metal silicide and Si becomes Shottky junction. When the Schottky junction is formed, contact resistance is increased; thus, on characteristics of a TFT are decreased. In order to improve the on characteristics, it is necessary to reduce the resistance of Si and to form the contact region of the metal silicide and Si to have ohmic contact.
In addition, there is a case where Si is used as a resistor in various circuits. However, when metal silicide is formed, metal silicide is formed over the entire surface of Si; thus, the resistance gets too low. Therefore, there has been a problem that a circuit area is increased when metal silicide of Si is used as the resistor.
There is also a method for removing metal or metal silicide over Si of a region where Si is used as the resistor; however, this method has a problem that the number of steps increases.
At present, a research on a submicron TFT has been carried out actively. However, with the use of a metal silicide method, it has been difficult to measure the resistance of an impurity region of Si when metal silicide is formed in source and drain regions.
Therefore, when on characteristics, which are intended, are not obtained in manufacturing a TFT, it has been difficult to examine whether the cause lies in that the resistance of Si is high or the cause lies in another aspect besides adequately low resistance of Si.
After manufacturing a TFT, as long as the resistance of Si can be measured, it is possible to estimate whether contact between metal silicide and Si has ohmic junction according to resistance of Si. When a TFT has extraordinary characteristics, it is possible to carry out feedback to a process immediately as long as it can be confirmed that the characteristics are beyond or under a standard value.